After 10 years, eventually Intel leaves FSB and replaces it with different path to connect processor and memory. Good bye FSB. One research has found that a couple of husband and wife will be similar one and another, whatever they are. May be the same in manner, the same of hobbies, etc.

Intel and AMD, they are not a couple….. indeed. Even we can say they are compete each other, they across each other. But our perspective may be different when we look at Intel latest processor micro architecture which called “Nehalem”, they are looked similar. Presenting Nehalem, Intel legitimate to leave FSB scheme (Front Side Bus) and switch to point-to-point connection which has high speed. Position of memory controller is not inside chipset, but it’s inside processor. AMD with Athlon 64 have applied this concept long time ago.

Intel can be told tracking back to AMD, but they have no choice. FSB which is used since Pentium Pro generation already hard to improve. Actually, FSB is the way to send or receive data between processor and memory, its need wide and speed way.

This time, highest FSB band is 1600MHz which gives bandwidth 12,8GB/second. As comparison thing, Hyper Transport which is used on Athlon64 can supply bandwidth as large as 41,6GB/second. Can you imagine it? What small bandwidth that can be supplied by FSB.

Because of that, Intel leaves FSB and change to the new way which is called QPI (Quick Path Interconnect). The QPI way of method more less similar with HT that used by Intel, it is point-to-point for high speed traffic data connection. In theory, QPI is able to be passed by data with bandwidth 24 – 32GB/second.

This approach can make possibility of memory controller to be placed inside processor, doesn’t like the older generation, where the memory controller placed on northbridge. Again this is Athlon way, and the ability has been proved.

Just want to reminding, memory controller job is to manage data depository which is need between processor and memory. At FSB system, memory controller exists in northbridge chipset. So that it will took so long time for processor when its need to get or save data, because its have to pass through FSB and then chipset. In Nehalem, memory controller placed inside processor, so that processor will move faster to reach memory when its need data. Plus with QPI connection from processor to memory, it’s free way traffic of data connection.

May be there is question appear, why doesn’t Intel do this from long time ago? The problem is the processor insufficient space. Especially on the old generation processor, Intel priority is another facility (it’s not memory controller) to be placed inside their processor.

Because of Intel has used 45nm fabrication now, there are many sufficient spaces available for memory controller inside processor. And this can be done without removing or decreasing cache capacity. Instead 45nm fabrication make possibility of Nehalem to have level 3 cache (L3 cache), in the past only available to processor in server class.

Conclusion:
Nehalem strategy is: enlarge cache size so that data isn’t too often entering memory system. Even its have to get in memory, the access can be faster because memory controller placed near processor and high speed data connection band.

With this strategy, Nehalem is indeed promising significant performance improvement. But, that’s just the theory, whether it will be reach, we have to be wait until Nehalem presents in fourth quarter at 2008.